Vertical split gate flash memory cell and method for fabricating the same

ABSTRACT

A vertical split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower portion of the trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The inter-gate dielectric layer is disposed between the floating gate and the control gate for insulation of the floating gate and the control gaze. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the control gate to serve as source and drain regions with the first doping region.

This application is a divisional of application Ser. No. 10/272,176,filed Oct. 15, 2002, which application(s) are incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to a semiconductor device andmethod for fabricating the same. More particularly, it relates to avertical split gate flash memory cell that increases integration withICs.

2. Description of the Related Art

Non-volatile memory, such as flash memory, stores data regardless ofelectrical power supplied, and reads and writes data by controlling athreshold voltage of a control gate. Conventionally, flash memoryincludes a floating gate and a control gate. The floating gate storescharge and the control gate reads and writes data. In addition, thefloating gate is located under the control gate and is not connected toexternal circuit, and the control gate connects to the word line. One ofthe advantages of flash memory is its capacity for block-by-block memoryerasure. Furthermore, memory erasure is fast, and normally takes just 1to 2 seconds for the complete removal of a whole block of memory.Therefore, in recent years, it has been widely applied to consumerelectronics devices, such as digital cameras, mobile phones, personalstereos, and laptops.

There is much interest in reducing the size of individual semiconductordevices to increase their density on an integrated circuit (IC) chip.This reduces size and power consumption of the chip, and allows fasteroperation. In order to achieve a memory cell with a minimum size, thegate length (line width) in a conventional transistor must be reduced todecrease the lateral dimension of the memory cell. However, theconventional process for fabricating flash memory usually usesphotomasks to define the devices. Since the precision of the photomasksis limited, misalignment usually occurs for devices with a smaller linewidth. This causes open circuits or short circuits, and the electricalproperties of the flash memory fail. Therefore, the device size of theconventional flash memory is limited by the design rule, so it isdifficult to shrink the device size. In addition, short channel effectand hot carrier effect occurs when the line width is shrink, therebyreducing the reliability of devices.

SUMMARY OF THE INVENTION

Accordingly, an object of the invention is to provide a novel verticalsplit gate flash memory cell to increase the integration of ICs bydecreasing the lateral dimension of the memory cell.

Another object of the invention is to provide a novel method forfabricating a vertical split gate flash memory cell to prevent shortchannel effect, thereby increasing the reliability of devices.

According to one aspect, the invention provides a split gate flashmemory cell. The memory cell includes a substrate, a floating gate, acontrol gate, a tunnel layer, a first doping region, and a second dopingregion. The floating gate is disposed in the lower portion of the trenchand insulated from the adjacent substrate by a floating gate oxidelayer. The control gate is disposed over the floating gate and insulatedfrom the adjacent substrate by a control gate oxide layer. Theinter-gate dielectric layer is disposed between the floating gate andthe control gate for insulation between the floating gate and thecontrol gate. The first doping region is formed in the substrateadjacent to the control gate and the second doping region is formed inthe substrate below the first doping region and adjacent to the floatinggate to serve as source and drain regions with the first doping region.The memory cell further includes an insulating layer, a conductive stud,and a gate structure. The insulating layer is disposed over the firstdoping region. The conductive stud is disposed on the control gate andinsulated from the first doping region by an insulating spacer. The gatestructure is disposed on the conductive stud to serve as a word line.

According to another aspect, the invention provides a method forfabricating a vertical split gate flash memory cell. First, a substratehaving a first trench and a second trench is provided. Next, aconformable floating gate oxide layer is formed over the sidewall andthe bottom of each lower portion of the trench. Next, a floating gate isfanned over the floating gate oxide layer in each of the lower portionof the trenches. Next, a tunnel oxide layer is formed on the floatinggate. Next, a conformable control gate oxide layer is formed over thesidewall of each upper portion of the trench. Next, a control gate isformed on the inter-gate dielectric layer. Next, ion implantation isperformed in the substrate adjacent to the floating gate to form asecond doping region. Finally, ion implantation is performed in thesubstrate adjacent to the control gate to form a first doping region.Moreover, after the control gate is formed, a conductive stud and aninsulating spacer are formed on the control gate, wherein the conductivestud is insulated from the first doping region by the insulating spacer.Next, an insulating layer is formed over the first doping region. Next,parts of the conductive stud, the insulating spacer, the control gate,the control gate oxide layer, the tunnel oxide layer, the floating gate,and the floating gate oxide layer in the fist trench are removed to forma third trench. Thereafter, an isolation structure is formed in thethird trench. Next, a plurality of gate structures is formed over theinsulating layer and the trenches.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading thesubsequent detailed description in conjunction with the examples andreferences made to the accompanying drawings, wherein:

FIG. 1 is a plane view showing a vertical split gate flash memory cellaccording to the present invention.

FIG. 2 is a cross-section showing a vertical split gate flash memorycell along A—A line in FIG. 1.

FIGS. 3-10 are cross-sections showing a method for fabricating avertical split gate flash memory cell according to the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a plane view of a vertical split gate flash memory cellhaving gate layer 222 and interconnect layer 230. FIG. 2 shows across-section of a vertical split gate flash memory cell along A—A linein FIG. 1. The memory cell includes a substrate 200, such as a p-typesilicon substrate, having a deep trench 207. A floating gaze is disposedin the lower portion of the trench 207. The floating gate 204 can bepolysilicon and is insulated from the adjacent substrate 200 by afloating gate oxide layer 202. A control gate 210 is disposed over thefloating gate 204 in the upper non on of the trench 207. Also, thecontrol gate 210 can be polysilicon and is insulated from the adjacentsubstrate 200 by a control gale oxide layer 208. A inter-gate dielectriclayer 206 is disposed between the floating gate 204 and the control gate210 for insulation of the floating gaze 204 and the control gate 210. Inthis invention, the inter-gate dielectric layer 206 has a thickness ofabout 100˜500 Å. Preferably, the inter-gate dielectric layer 206 has athickness of about 300 Å. A doping region 212, such as an n-type dopingregion, is formed in the substrate 200 adjacent to the control gate 210and another doping region 214, such as an n-type doping region, isformed in the substrate 200 adjacent to the floating gate 204. Dopingregion 212, 214 serve as drain region and source drain of the flashmemory cell, respectively, thereby forming two vertical channels (notshown) in the substrate 200 at both sides of the trench 207. Aninsulating layer 216, such as a silicon oxide layer, is disposed overthe doping region 212 and has openings (not shown) to expose the dopingregion 212. A conductive stud 220 is disposed on the control gate 210and insulated from the doping region 212 by an insulating spacer 218. Inthis invention, the conductive stud 220 can be polysilicon and theinsulating spacer can be silicon nitride. A plurality of gate structures227 are respectively disposed on the insulating layer 216 and conductivestud 220, wherein the gate structure 227 disposed on the conductive stud220 serves as a word line of the flash memory cell. The gate structure227 includes a gate 222, a gate spacer 226, and a cap layer 224. Thegate spacer 226 and cap layer 224 can be silicon nitride. An insulatinglayer 228, such as borophosphsilicate glass (BPSG), is deposited overthe insulating layer 216 and gate structure 227. Interconnect layer 230is formed over the insulating layer 228 and filled in the openings ofthe insulating layer 216 to connect with the doping region 212. In theinvention, the interconnect layer 230 can be tungsten or polysilicon.

FIGS. 3-10 shows cross-sections of a method for fabricating a verticalsplit gate flash memory cell according to the present invention. First,in FIG. 3, a substrate 200, such as p-type silicon substrate, isprovided. A pad oxide layer 201 and a silicon nitride layer 203 aresuccessively deposited on the substrate 200. Subsequently, lithographyand etching are performed on the silicon nitride layer 203 and the padoxide layer 201 to form openings (not shown) and expose the substrate200. Next, the exposed substrate 200 under the openings is etched byanisotropic etching, such as dry etching, using the silicon nitridelayer 203 as a mask to form a plurality trenches. In order to simplifythe diagram, only two trenches 205, 207 are shown.

In FIG. 4, conformable floating gate oxide layers 202 are respectivelyformed over the sidewall and the bottom of the lower portion of thetrenches 205, 207 by thermal oxidation or other conventional deposition.Thereafter, floating gates 204 are respectively formed ova the floatinggate oxide layers 202 in the lower portion of the trenches 205, 207. Inthis invention, a polysilicon layer (not shown) is deposited on thesilicon nitride layer 203 and filled in the wenches 205, 207. Next, thepolysilicon layer is etched back to leave part of a polysilicon layer ineach of the trenches 205, 207, to serve as floating gates. The height ofthe floating gate oxide layer is substantially equal to the remainedpolysilicon layer 204.

Next, a conformable silicon oxide layer (not shown) is formed over thesilicon nitride 203 and the surface of the trenches 205, 207 byconventional deposition, such as chemical vapor deposition (CVD).Subsequently, the silicon oxide layer over the silicon nitride 203 andthe sidewall of the trenches 205, 207 is removed to leave a siliconoxide layer 206 on the floating gate 204. The remaining silicon oxidelayer 206 serves as a inter-gate dielectric layer, which has a thicknessof about 100˜500 Å.

Also, conformable control gate oxide layers 208 are fanned over thesidewall of the upper portions of the trenches 205, 207 by thermaloxidation or other conventional deposition. Thereafter, a control gaze210, such as polysilicon, is formed on the inter-gate dielectric layer206. As shown in FIG. 4, the height of the control gate 210 issubstantially equal to the control gate oxide layer 208 and bath arelower than the top surface of the substrate 200.

Next, in FIG. 5, after the control gate 210 is formed, a conductive stud220 and an insulating spacer 218 are formed on the control gate 210. Inthis invention, the conductive stud can be polysilicon and theinsulating spacer 218 can be silicon nitride.

Next, in FIG. 6, parts of the conductive stud 220, the insulating spacer218, the control gate 210, the control gate oxide layer 208, the layerinter-gate dielectric layer 206, the floating gate 204, and the floatinggate oxide layer 202 in the trench 205 are removed by lithography andetching to form a trench 211. Thereafter, silicon oxide (not shown) isfilled in the trench 211 by CYD, such as high-density plasma CVD(HDPCVD), to form an isolation structure 213.

Next, in FIG. 7, after the silicon nitride layer 203 is removed, ionimplantation is performed in the substrate 200 adjacent to the floatinggate 204 to form a doping region 214, such as an n-type doping region.Subsequently, ion implantation is performed again in the substrate 200adjacent to the control gate 210 to form a doping region 212, such as ann-type doping region. These n-type doping region 212, 214 serve as drainregion and source region of the vertical split gate flash memory cell ofthe invention. In addition, the conductive stud 220 is insulated fromthe n-type doping region 212 by the insulating spacer 218. Next, aninsulating layer 216, such as a silicon oxide layer, is deposited on then-type doping region 212 by conventional deposition, such as CVD, tomake its height substantially level with the conductive stud 220 andinsulating spacer 218.

Next, in FIG. 8, a plurality of gate structures 227 are formed over theinsulating layer 216 and the trenches 205, 207. Each gate structure 227includes a gate 222, a gate spacer 226, and a cap layer 224, wherein thegate spacer 226 and the cap layer 224 can be silicon nitride.

Next, in FIG. 9, an insulating layer 228, such as BPSG, is depositedover the insulating layer 216 and gate structures 227. Finally, FIG. 10shows a cross-section along B—B line in FIG. 1, in which the insulatinglayer 228 is patterned by lithography and etching to expose part ofdoping region 212 in the substrate 200. Next, an interconnect layer 230is formed over the gate structures 227 and connected with the exposeddoping region 212. In this invention, the interconnect layer 230 can betungsten or polysilicon.

Since the channel of the vertical split gate flash memory cell accordingto the invention is vertical, the integration of ICs can be effectivelyincreased due to decreased lateral dimension of the memory cell comparedwith the prior art. Moreover, in the invention, the channel length isnot based on the line width, but based on the depth of the trench. Thatis, the short channel effect or hot carrier effect as mentioned in theprior art cannot occur even when line width is shrunk. Therefore, thereliability of the devices can be increased.

The foregoing description has been presented for purposes ofillustration and description. Obvious modifications or variations arepossible in light of the above teaching. The embodiments were chosen anddescribed to provide the best illustration of the principles of thisinvention and its practical application to thereby enable those skilledin the art to utilize the invention in various embodiments and withvarious modifications as are suited to the particular use contemplated.All such modifications and variations are within the scope of thepresent invention as determined by the appended claims when interpretedin accordance with the breadth to which they are fairly, legally, andequitably entitled.

What is claimed is:
 1. A method for fabricating a vertical split gateflash memory cell, comprising: providing a substrate having a firsttrench and a second trench; forming a conformable floating gate oxidelayer over the sidewall and the bottom of each lower portion of thefirst and second trenches; forming a floating gate over the floatinggate oxide layer in each portion of the first and second trenches;forming a inter-gate dielectric layer on the floating gate; forming aconformable control gate oxide layer over the sidewall of each upperportion of the first and second trenches; forming a columnar controlgate on the inter-gate dielectric layer and fully below the first andsecond trenches; performing ion implantation in the substrate adjacentto the floating gate to form a second doping region; and performing ionimplantation in the substrate adjacent to the control gate to form afirst doping region.
 2. The method as claimed in claim 1, wherein, afterforming the control gate, further: forming a conductive stud and aninsulating spacer on the control gate, wherein the conductive stud isinsulated from the first doping region by the insulating spacer, formingan insulating layer over the first doping region; removing part of theconductive stud, the insulating spacer, the control gate, the controlgaze oxide layer, the inter-gate dielectric layer, the floating gate,and the floating gate oxide layer in the first trench to form a thirdtrench; forming an isolation structure in the third trench; and forminga plurality of gate structures over the insulating layer and the firstand second trenches.
 3. The method as claimed in claim 2, wherein theconductive stud is polysilicon.
 4. The method as claimed in claim 2,wherein the insulating spacer is silicon nitride.
 5. The memory cell asclaimed in claim 2, wherein the insulating layer is silicon oxide. 6.The method as claimed in claim 2, wherein the isolation structure ishigh-density plasma oxide.
 7. The method as claimed in claim 2, whereineach of the gate structures includes a gate, a gate spacer, and a caplayer.
 8. The method as claimed in claim 7, wherein the gate spacer andthe cap layer are silicon nitride.
 9. The method as claimed in claim 1,wherein the substrate is a p-type silicon substrate.
 10. The method asclaimed in claim 9, wherein the first and second doping regions aren-type doping regions.
 11. The method as claimed in claim 1, wherein thefloating gate is polysilicon.
 12. The method as claimed in claim 1,wherein the control gate is polysilicon.
 13. The method as claimed inclaim 1, wherein the inter-gate dielectric layer has a thickness ofabout 100˜500 Å.
 14. The method as claimed in claim 1, wherein theheight of the floating gate oxide layer is substantially equal to thefloating gate.
 15. The method as claimed in claim 1, wherein the heightof the control gate oxide layer is substantially equal to the controlgate.